Transient analysis of a CMOS inverter driving resistive interconnect
نویسندگان
چکیده
Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are characterized by the th power law model. In order to emphasize the nonlinear behavior of a CMOS inverter, the interconnect is modeled as a lumped load. The propagation delay of a CMOS inverter is characterized for both a fast ramp and a slow ramp input signal. The waveform of the output voltage based on these analytic equations is quite close to SPICE assuming a fast ramp input signal. The accuracy of the propagation delay model for both fast ramp and slow ramp input signals is within 7% as compared to SPICE simulations.
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